**NoC Implementation of AES Algorithm: A Survey**

Harish Babu L,Savitha C and Dr. M Z Kurian,SSIT, Tumkur,India##### ABSTRACT

Network on chip (NoC) is the scalable platform where billion transistors have been integrated on to a single chip. NoC architecture is a m¡ßn mesh of processing elements where resources are placed on the slots formed by the switches. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, or any other intellectual property (IP) block, which fits into the available slot and complies with the interface of the NoC. The NoC architecture is an on-chip communication infrastructure which comply OSI protocol stack.

Existing Algorithm has a deadlock issue and head of line blocking problem which reduces the efficiency of system. Here a modified routing logic has been proposed and the same will be developed for NoC architecture to overcome drawbacks of algorithm. Here an Advanced Encryption Standard (AES) blocks will be used for the designing of the Network-on-Chip architecture. And the survey of the related researches has been carried out to support the design.**Design and Implementation LFSR using Reversible Logic: a Survey**

Kavya Shree C,Praveen Kumar Y G and Dr. M Z Kurian,SSIT, Tumkur,India##### ABSTRACT

Reversible logic has emerged as one of the most important approaches for the optimization of power in low power VLSI design. They are also the basic requirement for the emerging field of the Quantum computing having their applications in the areas such as Digital Signal Processing, Nano-Technology, Cryptrography etc. It means performing computation in such a way that any previous state of the computation can always be reconstructed with given description of the current state. Here Reversible logic is used for designing a Linear Feedback Shift Register (LFSR). LFSR is a shift register that, when applied with the clock, shift the signal through the register from one bit to the next most-significant bit. Outputs from some of the register are combined through the exclusive-OR configuration and feedback mechanism is formed. Linear Feedback Shift Register can be formed by performing exclusive-OR on the outputs of two or more of the flip-flops together and feeding those outputs back into the input of one of the flip-flops. As a prior work, literature survey has been done.**FPGA BASED EMBEDDED SYSTEM TO CONTROL ELECTRICAL DEVICES THROUGH ANDROID MOBILE**

Catherine Seagulll and Samson Immanuel,Karunya University, India##### ABSTRACT

Field programmable gate array is a semiconductor device that serves as an ideal fit for various industries in today¡Çs market owing to its various mixes of configurable embedded SRAM, high-speed transceivers, logic blocks with memory unit and routing. This paper presents the design and implementation of a FPGA based embedded system to control electrical devices through Android mobile. Bluetooth is implemented as the mode of transmission between the sources, making use of Bluetooth feature that prevails in most of the mobile phones. Android platform is also one of the fastest moving environments that make it fit for this mobile generation and its future processing.**Design and Analysis of Low-Power High-Speed Clocked Digital Comparator**

Sameer Thakre and Dr. Pankaj Srivastavay, ABV-Indian Institute of Information Technology and Management, Gwalior,India##### ABSTRACT

The need for low power, area efficient and high speed comparator is pushing towards the use of clocked digital comparator which maximize speed and power efficiency. As CMOS technology scales down, various short channel effects arises which increases the leakage current due to low threshold voltage and waste some percentage of power as leakage power. This paper presents detail survey of low power techniques and also proposed a new technique which modified the clocked digital comparator by adding some sleep transistors with appropriate W=L ratio for low-power and fast operation. Various Post layout simulation result with 90nm, 65nm and 45nm CMOS technology at supply voltage of 1.2 V confirms the analysis results. The result shows that in the proposed clocked Digital comparator both the Average power dissipation, delay time are significantly reduced. For maximum clock frequency of 500 MHz and offset voltage of 0.6 V, the proposed design-I comparator consumes 5.691W, 3.056 W and 2.276 W at 90nm, 65nm and 45nm respectively.**DESIGN AND IMPLEMENTATION OF POWER OPTIMIZED 64 BIT FLOATING POINT ALU EMPLOYING BLOCK ENABLING TECHNIQUE**

B.N.V.Amar Surendra Babu ,Y.Syamala and k.Srilakshmi,Gudlavalleru Engineering College, Gudlavalleru, India##### ABSTRACT

The 64 bit floating point ALU can be used as a coprocessor to a main processor that allowed an embedded system to perform floating point calculations more efficiently and increasing the overall speed of a system. The density and power consumption of processors are limited primarily by power consumption concerns. Hence in this paper implementation of a 64 bit floating point ALU called Math coprocessor with block enabling technique is proposed to decrease the power consumption of the processor and this value is compared with the floating point ALU without block enabling technique. All the modules in floating point unit are realized using verilog HDL. This designed floating point unit is mapped on to vertex5 and vertex 6 low power FPGAs. The simulation is done using Isim simulator and synthesis is carried out using XILINX ISE synthesis tool on the XILINX-14.7 platform. This floating point ALU achieves maximum frequency of 207.168 MHZ with a dynamic power dissipation of 38 mw when operated at a clock frequency of 10MHZ. Finally, it was observed that 12% reduction in dynamic power consumption was achieved by using block enabling technique to the floating point ALU.**OVERVIEW OF LOW POWER DESIGN AND VLSI CRISES**

Devarsh Bharambe Marathwada Institute of Technology, Aurangabad (MS), India.##### ABSTRACT

The growing market of battery-operated portable applications like laptop, mobile etc requires microelectronic devices with low power consumption. As transistor size continues to shrink and as need for more complex chips increases, power management of the chip is one of the key challenges in VLSI industry. The manufacturers are looking for low power designs because providing adequate cooling and packaging increases the cost and limits the functionality of the device. This paper surveys the optimization techniques used to reduce power consumption in CMOS at all the levels of the design flow.The VLSI design productivity crisis, that is, the fact that the number of available transistors grows much faster than the ability to design them meaningfully, has become the greatest threat to the growth of semiconductor industry. The cost-performance is rapidly improved as devices are scaled down. This is the reason why the miniaturization has been pursued persistently for these thirty years and will be pursued in the future.**An FPGA Implementation of High Speed and Area Efficient Double-Precision Floating Point Multiplier Using Urdhva Tiryagbhyam Technique**

Y. Srinivasa Rao,T. Subhashini and Dr. M. Kamaraju,Gudlavalleru Engineering College,Gudlavalleru, India##### ABSTRACT

Floating-point arithmetic is ever-present in computer systems.Every computer language has supports a floating-point data types. Most of the computer compilers call upon floating-point algorithms from time to time for execusion of the floating-point arithmetic operations and every operating system must respond virtually for floating-point exceptions such as underflow and overflow. The double-precision floating arithmetic is mainly used in the digital signal processing (filters, FFTs) applications, numerical applications and scientic applications. The double-precision floating arithmetic supports the addition, subtraction, multiplication, division, and square root. Among the all arithmetic operations, multiplication is widely used and most complex arithmetic operation. The double-precision (64-bit) floating point multiplier has a 1-bit sign bit, 11-bits exponent bits and 52-bits mantissa bits. The double-precision floating-point multiplier requires a large 52x52 mantissa multiplication to get the final result. The mantissa multiplication exits as a limit on both area and speed bounds of multiplication operation. The proposed work presents a novel way to reduce this large mantissa multiplication. The Urdhva Tiryagbhyam technique allows using less amount of multiplication hardware compared to the traditional method. In traditional method adding of the partial products are separately done and it takes more time in comparision with the proposed metdod. In proposed method the partial products are concurrently added with the multiplication operaton and it canreduce the time delay. The double-precision floating multiplier is implemented using VerilogHDL with Xilinx ISE tools on Virtex-5 FPGA.